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BRAM inference for Xilinx FPGAs · Issue #17 · alexforencich/verilog-axi · GitHub
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Incorrect RAM size while using ram_style = "ultra" | "block" on 2016.4
Support controlling ram_style for decoupled mode memories · Issue #82 · Xilinx/finn · GitHub
VIVADO 2014.1 does not infer LUTRAM with (* ram_style = "distributed" *) in RTL
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Issues about folding factors settings before hardware generation · Discussion #658 · Xilinx/finn · GitHub
Support controlling ram_style for decoupled mode memories · Issue #82 · Xilinx/finn · GitHub
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